Latches and flip-flops are widely used in all types of electronic devices for counting, sampling, and storage of data. There are a number of different types of flip-flops named after their primary function, such as D-type flip-flops (data), J-K flip flops (J and K inputs), and R-S flip-flops (having R and S latches, standing for “reset: and “set”. D flip-flops are a clocked flip-flop having a one clock pulse delay for its output.
Conventional flip-flops, such as D-type, can be used to detect the logic state of an asynchronous digital signal with timing relative to the clock signal that is non-periodic.
For example, as shown in FIG. 1, a synchronous signal can be applied to the clock input (CLK) 105 of flip-flip 110, and a digital logic level of the asynchronous signal (the inverted output —Q of the flip-flop) to be detected is directed to the D input. The output signal is subsequently inverted on the Q output. Afterward, the flip-flop changes state whenever the clock signal is changed, as long as the reset signal is tied permanently to ground.
When there are multiple systems linked together, and the systems operate at different frequencies, it has long been a problem of designers to attempt a synchronization of the systems. It is a well-known way to synchronize such systems by synchronizing one of the signals with a local clock generator, by the use of a flip-flop.
However, the above solution to the synchronization problem is not perfect, as the operating conditions of the flip-flops can be violated because hold times and setup times are not always consistent with the specifications (such as provided in the data sheets) of the flip flops used. The violation of the flip-flops can cause them to go into an unstable (metastable) state that can affect the entire operation of the linked systems. Metastability can occur when both inputs to a latch are set at a logic high (11) and are subsequently set at a logic low (00).
Metastability can cause the latch outputs to oscillate unpredictably in a statistically known manner. While theoretically it is possible for the latch outputs to oscillate in a statistically known manner, in reality the latch will randomly shift and arrive at random output values. Such metastable values are then detected by other circuitry as different logic states.
In circuit design, it is necessary for an engineer to determine what influence metastable states may have in a particular design, and provide ways to overcome the bad effects that metastability could have on a circuit.
It has also been recognized that the output of a metastable flip-flop circuit is sufficiently random. Thus, the instant inventor submits that the randomness of the metastable flip-flop is sufficiently random to build a random number generator.
FIG. 1 also shows a diagram of a flip-flop 109 realized with cross connected NAND gates 108,110. This flip-flop receives its both data inputs from clock oscillator 105 through the clock input 106 of flip-flop 109, which shapes the clock signal to square-wave. The Q output 107 is connected to both of the NAND gates 108, 110 via delay devices, 112,114, respectively. If the two NAND gates 108,110 were truly identical, there would be no need for the delay devices to achieve the highest probability to get the flip-flop 109 to become metastable. However, the NAND gates will ordinarily differ somewhat, and their speed difference will influence the number of times metastability occurs in a time interval.
In VLS integrated circuits there have been attempts at tunable delay by using single tapped-buffer chains, but their implementation has not been practical. The delay resolution was too course for the dynamic fine tuning required to achieve the highest frequencies at which metastability occurs. Delays were also designed by the introduction of long wires of various lengths, which increased design expense and was found to be difficult to control using automatic layout tools and standard element libraries.